Схемы параллельно-последовательного и последовательно-параллельного преобразования (Serdes) SN65LVDS95DGG .

Передатчик , 3В до 3.6В, TSSOP-48

The SN65LVDS95DGG is a LVDS Serdes (Serializer/Deserializer) Transmitter contains three 7-bit parallel-load serial-out shift registers, a 7x clock synthesizer and four low-voltage differential signalling (LVDS) line drivers in a single integrated circuit. These functions allow 21-bit of single-ended LVTTL data to be synchronously transmitted over 4 balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS96. When transmitting, data bits D0 through D20 are each loaded into registers of the SN65LVDS95 on the rising edge of the input clock signal. The frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN. The data bus appears the same at the input to the transmitter and output of the receiver with data transmission transparent to the user(s).

• Suited for point-to-point subsystem communication with very low EMI
• No external components required for PLL
• Replacement for the National DS90CR215
• 21 Data channels/clock in low-voltage TTL and 3 data channels/clock out low-voltage differential
• 5V Tolerant data inputs
• With rising clock edge triggered inputs
• Bus pins tolerate 6kV HBM ESD
• Consumes <1mW when disabled
• 3:21 Data channel compression at up to 1.428Gigabits/s throughput
• Green product and no Sb/Br

Области применения

Промышленное, Обработка Сигнала, Время и Расчет Времени, Связь и Сеть