Схемы параллельно-последовательного и последовательно-параллельного преобразования (Serdes) SN65LVDS93DGG

Передатчик , 3В до 3.6В, TSSOP-56

The SN65LVDS93DGG is a Serdes (Serializer/Deserializer) Transmitter contains four 7-bit parallel- load serial-out shift registers, a 7x clock synthesizer and five low-voltage differential signalling (LVDS) drivers in a single integrated circuit. These functions allow 28-bit of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS94. When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal. The rising or falling edge of the clock can be selected via the clock select pin. The frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices. The four serial streams and a phase-locked clock are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN. The SN65LVDS93 requires no external components and little or no control.

• Suited for point-to-point subsystem communication with very low EMI
• Selectable rising or falling clock edge triggered inputs
• No external components required for PLL
• Replacement for the DS90CR285
• 28 Data channels/clock in low-voltage TTL and 4 data channels/clock out low-voltage differential
• Bus pins tolerate 6kV HBM ESD
• 5V Tolerant data inputs
• Consumes <1mW when disabled
• Wide phase-lock input frequency range 20 to 68MHz
• Green product and no Sb/Br

Области применения

Промышленное, Потребительская Электроника, Медицинское, Переносные Устройства, Время и Расчет Времени, Связь и Сеть