Процессоры и контроллеры цифровых сигналов (DSP, DSC) DSPIC33FJ16GS504-I/PT

• Code-efficient (C and assembly) architecture
• Two 40-bit wide accumulators
• Single-cycle (MAC
• MPY) with dual data fetch
• Single-cycle mixed-sign MUL Plus hardware divide
• Up to four PWM pairs with independent timing
• Dead time for rising and falling edges
• Programmable fault inputs
• Flexible trigger configurations for ADC conversions
• 10-bit Digital-to-analogue converter (DAC) for each comparator

• Three 16-bit and one 32-bit timer
• counter
• Peripheral pin select (PPS) to allow function remap
• I²C™ Module (up to 1Mbps) with SMBus support

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