Микросхемы и комплектующие 74LV165AD,112

Регистр сдвига , семейство LV, 74LV165, Параллельный в Последовательный, 1 Элемент, 8 бит, SOIC

The 74LV165AD is a 8-bit parallel-load or serial-in Shift Register with complementary serial outputs (Q7 and Q7\) available from the last stage. When the parallel-load input (PL\) is low, parallel data from the inputs D0 to D7 are loaded into the register asynchronously. When input PL\ is high, data enters the register serially at the input DS. It shifts one place to the right (Q0 ->Q1 ->Q2) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the output Q7 to the input DS of the succeeding stage. The clock input is a gate-OR structure which allows one input to be used as an active low clock enable input (CE\) input. The pin assignment for the inputs CP and CE\ is arbitrary and can be reversed for layout convenience. The low-to-high transition of the input CE\ should only take place while CP high for predictable operation.

• Synchronous parallel-to-serial applications
• Synchronous serial input for easy expansion
• Latch-up performance exceeds 250mA
• CMOS low power consumption
• 5.5V Tolerant inputs/outputs
• Direct interface with TTL levels
• Power-down mode

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Промышленное, Потребительская Электроника, Компьютеры и Периферия