Микроконтроллеры широкого назначения AT89C51CC01CA-SLSUM

• 80C51 Core architecture
• Boot code section with independent lock bits
• In-system programming by on-chip boot program (CAN, UART) and IAP capability
• 14-sources 4-level Interrupts
• Three 16-bit timers
• counters
• Full duplex UART compatible 80C51
• Five ports - 32 + 2 digital I
• O lines
• Five-channel 16-bit PCA

• Double data pointer
• 21-bit Watchdog timer (7 Programmable bits)
• 10-bit resolution Analog-to-digital converter (ADC) with 8 multiplexed Inputs
• On-chip Emulation logic (Enhanced hook system)
• Power saving modes - Idle mode, Power-down mode
• Maximum crystal frequency 40MHz in X2 mode
• Fully compliant with CAN Rev2.0A and 2.0B
• Optimized structure for communication management (Via SFR)
• Time triggered communication
• Autobaud and listening mode
• Programmable automatic reply mode
• 1Mbps Maximum transfer rate at 8MHz crystal frequency in X2 mode

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