Логическая ИС SN74LV595APWR .

Регистр сдвига , семейство LV, 74LV595, Последовательный в Параллельный, 1 Элемент, 8 бит, TSSOP

The SN74LV595APWR is a 8-bit serial-in parallel-out Shift Register feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for the shift and storage registers. The shift register has a direct overriding clear (SRCLR\) input, serial (SER) input and serial outputs for cascading. When the OE\ input is high, the outputs are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. This low-drive CMOS device can be used for a multitude of bus interface type applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on the outputs. The inputs are 5V tolerant allowing for down translation to VCC.

• Support mixed-mode voltage operation on all ports
• Ioff Supports live insertion, partial power-down mode and back-drive protection
• Shift register has direct clear
• Latch-up performance exceeds 250mA per JESD 17
• Green product and no Sb/Br

Области применения

Связь и Сеть, Управление Питанием, Компьютеры и Периферия