Логическая ИС SN74LV574APW

Триггер , 74LV574, D, 5.7 нс, 205 МГц, 16 мА, TSSOP

The SN74LV574APW is an octal edge-triggered D-type Flip-flop with 3-state outputs. It is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. On the positive transition of the clock input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pull-up components. OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

• Supports mixed-mode signal operation on all ports
• Ioff Supports partial-power-down mode operation
• Latch-up performance exceeds 250mA per JESD 17
• Green product and no Sb/Br

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