Логическая ИС SN74LV4046APW

Схема ФАПЧ , 38МГц, 3В до 5.5В, TSSOP-16

The SN74LV4046APW is a high-speed silicon-gate CMOS PLL with VCO that is pin compatible with the CD4046B and the CD74HC4046. The device is specified in compliance with JEDEC Std 7. The SN74LV4046A is a phase-locked loop (PLL) circuit that contains a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and PC3). A signal input and a comparator input are common to each comparator. The signal input can be directly coupled to large voltage signals or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the SN74LV4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear operational amplifier techniques. Various applications include telecommunications, digital phase-locked loop and signal generators.

• Excellent VCO frequency linearity
• VCO-inhibit control for ON/OFF keying and for low standby power consumption

Области применения

Связь и Сеть, Управление Питанием, Обработка Сигнала