Логическая ИС SN74LS377N

Триггер , 74LS377, D, 17 нс, 40 МГц, 8 мА, DIP

The SN74LS377N is an octal D-type Flip-flop with clock enable. It utilizes TTL circuitry to implement D-type flip-flop logic with an enable input. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G\ input. It is guaranteed to respond to clock frequencies ranging from 0 to 30MHz while maximum clock frequency is typically 40MHz. Typical power dissipation is 10mW per flip-flop.

• Individual data input to each flip-flop
• TTL Input and output

Области применения

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