Логическая ИС SN74LS165AD

Регистр сдвига , 74LS165, Параллельный в Последовательный, 1 Элемент, 8 бит, SOIC, 16 вывод(-ов)

The SN74LS165AD is a 8-bit parallel-load serial-out Shift Register that shifts the data in the direction of QA toward QH when clocked. parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD\) input. These registers also feature gated clock (CLK) inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design. clocking is accomplished through a two-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking and holding either clock input low with SH/LD\ high enables the other clock input. clock inhibit (CLK INH) should be changed to the high level only while CLK is high. Parallel loading is inhibited as long as SH/LD\ is high. Data at the parallel inputs are loaded directly into the register.

• Complementary outputs
• Direct overriding load (data) inputs
• Gated clock inputs
• Parallel-to-serial data conversion
• Green product and no Sb/Br

Области применения

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