Логическая ИС SN74LS138D

Decoder / Demultiplexer , LS Family, 3:8, 4.75 V to 5.25 V, SOIC-16

The SN74LS138D is a 3-to-8 Decoder/Demultiplexer designed to be used in high-performance memory decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the Schottky-clamped system decoder is negligible. The LS138 decodes one of eight lines dependent on the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter.

• Designed specifically for high-speed
• Memory decoders
• Data transmission systems
• 3 Enable inputs to simplify cascading and/or data reception
• Schottky-clamped for high performance
• Green product and no Sb/Br

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