Логическая ИС CD74HC595M

Регистр сдвига , 74HC595, Последовательный в Параллельный, 1 Элемент, 8 бит, SOIC, 16 вывод(-ов)

The CD74HC595M is a 8-bit Shift Register with 3-state output registers. It contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage registers. The shift register has a direct overriding clear (SRCLR\) input, serial (SER) input and serial output for cascading. When the OE\ input is high, the outputs are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

• High-current 3-state outputs can drive up to 15 LSTTL loads
• Shift register has direct clear
• Typical tpd = 14ns
• ±6mA Output drive at 5V
• 1µA Maximum low input current
• 80µA Maximum low power consumption
• Green product and no Sb/Br

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