Линии задержки/хронирующие элементы SY100EP195VTG

DELAY LINE , PROG, 1024, 12.2NS, TQFP-32

The SY100EP195VTG is a high-speed low-skew PECL/ECL 1:4 precision Fanout Buffer with 2:1 mux input accepts a single-ended PECL/ECL source (CLK1) and a differential PECL/ECL/HSTL source (CLK0). All I/O pins are 100K EP PECL/ECL logic compatible. AC performance is guaranteed over the industrial -40 to +85°C temperature range and 3.3 to 5V supply voltage. This device will operate in PECL/LVPECL or ECL/LVECL mode. For clock applications, the high-speed design combined with an extremely fast rise/fall time of less than 225ps produces a toggle frequency as high as 2.5GHz (~400mVPP swing). A VBB output reference pin is available for AC-coupled and single-ended input applications. In addition, a synchronous output enable function is provided. For applications that require a different I/O combination, consult Micrel's website and choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators and clock dividers.

• VBB reference for AC-coupled or single-ended applications
• Output enable/disable function

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