Линии задержки/хронирующие элементы DS1023S-50+

Линия задержки , 256 тактов, 500пс задержка/такт, 127.5нс общая задержка, 4.75В до 5.25В питание

The DS1023S-50+ is an 8bit programmable timing element (delay line) in 16 pin WSOIC package. The internal delay line architecture has been revised to allow clock signals to be delayed for full period or more. Combined with an on-chip reference delay (to offset the inherent or 'step zero' delay of the device) clock phase can now be varied over the full 0°-360° range. On-chip gating is provided to allow the device to provide a pulse width modulated output, triggered by the input with duration set by the programmed value. Alternatively the output signal may be invertedon-chip, it allows the device to perform as a free-running oscillator if the output is (externally) connected to the input. The device programming is identical to the DS1020/DS1021. However, the serial clock and data pins are shared with three of the parallel input pins.

• Supply voltage range is 4.75V to 5.25V
• Operating temperature range from 0°C to 70°C
• Step size of 0.5ns
• Maximum delay time of 127.5ns, minimum input pulse width is 20ns
• Maximum deviation of ±2ns
• Maximum input frequency is 25MHz, maximum output frequency is 22MHz
• On-chip reference delay
• Configurable as delay line, pulse width modulator or free-running oscillator
• Can delay clocks by a full period or more, parallel or serial programming
• Features monotonicity

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