ИС интерфейса LVDS SN65MLVD206D

Буфер , 3В до 3.6В, SOIC-8

The SN65MLVD206D is a Half-duplex Transceiver optimized to operate at signaling rates up to 200Mbps. All parts comply with the multipoint low-voltage differential signaling M-LVDS standard TIA/EIA-899. This circuit is similar to their TIA/EIA-644 standard compliant LVDS counterparts with added features to address multipoint applications. The driver output has been designed to support multipoint buses presenting loads as low as 30R and incorporates controlled transition times to allow for stubs off of the backbone transmission line. This device has type-1 and type-2 receivers that detect the bus state with as little as 50mV of differential input voltage over a common-mode voltage range of -1 to 3.4V. The type-1 receivers exhibit 25mV of differential input voltage hysteresis to prevent output oscillations with slowly changing signals or loss of input. Type-2 receivers include an offset threshold to provide a known output state under open-circuit, idle-bus and other faults conditions.

• Controlled driver output voltage transition times for improved signal quality
• Bus pins high impedance when disabled or VCC
• Meets or exceeds the M-LVDS standard TIA/EIA-899 for multipoint data interchange
• M-LVDS Bus power up/down glitch free
• Green product and no Sb/Br

Области применения

Промышленное, Обработка Сигнала, Время и Расчет Времени, Потребительская Электроника, Связь и Сеть