ИС интерфейса LVDS SN65LVDT101DGK

Транслятор уровня напряжения , LV семейство, 2 входа, 12мкА, 630пс, 2ГБ/с, 3В до 3.6В, MSOP-8

The SN65LVDT101DGK is a 2Gbps LVDS/LVPECL/CML to LVDS Repeater/Translator accepts low-voltage differential signaling (LVDS), positive-emitter-coupled logic (PECL) or current-mode logic (CML) input signals at rates up to 2Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter. The outputs of SN65LVDT101 are LVDS levels as defined by TIA/EIA-644-A. It includes an 110R differential line termination resistor for less board space, fewer components and the shortest stub length possible. They do not include the VBB voltage reference found in the SN65LVDS101. VBB provides a voltage reference of typically 1.35V below VCC for use in receiving single-ended input signals and is particularly useful with single-ended 3.3V PECL inputs. When VBB is not used, it should be unconnected or open.

• Total Jitter <65ps
• Low-power alternative for the MC100EP16
• Low 100ps maximum part-to-part skew
• Inputs electrically compatible with LVPECL, CML and LVDS signal levels
• LVDT Integrates 110R terminating resistor
• 25mV of Receiver input threshold hysteresis over 0 to 4V input voltage range
• Green product and no Sb/Br

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