Генераторы частоты CDC3RL02YFPR

Clock Buffer , 52 MHz, 2.3V-5.5V supply, 2 Outputs, DSBGA-8

The CDC3RL02YFPR is a two-channel clock Fan-out Buffer ideal for portable end-equipment, such as mobile phones, that requiring clock buffering with minimal additive phase noise and fan-out capabilities. It buffers a single master clock, such as a temperature compensated crystal oscillator (TCXO) to multiple peripherals. The device has two clock request inputs (CLK_REQ1 and CLK_REQ2), each of which enable a single clock output. The CDC3RL02 accepts square or sine waves at the master clock input (MCLK_IN), eliminating the need for an AC coupling capacitor. The smallest acceptable sine wave is a 0.3V signal (peak-to-peak). It has been designed to offer minimal channel-to-channel skew, additive output jitter and additive phase noise. The adaptive clock output buffers offer controlled slew-rate over a wide capacitive loading range which minimizes EMI emissions, maintains signal integrity and minimizes ringing caused by signal reflections on the clock distribution lines.

• Low additive noise
• 0.37ps RMS Output Jitter
• Limited output slew rate for EMI reduction
• Adaptive output stage controls reflection
• ESD Performance exceeds JESD 22
• Green product and no Sb/Br

Области применения

Компьютеры и Периферия, Автоматизация и Управление Процессами, Считывание и Контрольно-измерительная Аппаратура, Управление Питанием